The present invention relates to a semiconductor memory device; and, more particularly, to a refresh operation of a semiconductor memory device.
Generally, a semiconductor memory device is a semiconductor device for storing a great amount of data. This semiconductor memory device is divided into a data storage area for storing data and a peripheral and input/output area for accessing the data stored in the data storage area. The data storage area is provided with a plurality of unit cells, each of which stores a single datum. The peripheral and input/output area is provided with a variety of circuits for effectively accessing data of the unit cells in the data storage area.
A dynamic random access memory (DRAM), a most widely used semiconductor memory device, is designed in a manner that one unit cell is implemented with a single MOS transistor and a single capacitor. In order to store more data, the MOS transistor and capacitor constituting each of the unit cells in the data storage area are manufactured in as small a size as possible.
Since a semiconductor memory device, such as a DRAM, uses a capacitor as a basic component of data storage, the data stored therein should be refreshed at regular intervals. This is because the charge amount stored in the capacitor gets lost as time goes by, in view of the nature of the capacitor. The semiconductor memory device performs the operation of supplementing the lost amount of charge before the charge amount stored in the capacitor constituting the unit cell decreases less than a predetermined amount. This operation is called a refresh operation.
The refresh operation includes an auto refresh operation and a self refresh operation. The auto refresh operation refers to an operation that takes a refresh command from outside of the semiconductor memory device, internally generates an address to be refreshed, and then performs the refresh operation during the data access of the semiconductor memory device. The self refresh operation refers to an operation that accepts a start command related to the self refresh from the outside of the semiconductor memory device, internally generates a refresh command and an address to be refreshed, and then executes the refresh operation when the semiconductor memory device is not performing a data access operation, such as a power down mode and the like.
In order to know if the self refresh or auto refresh operation is being properly performed at predetermined intervals, it is required to check whether there is any change by data access after the refresh operation is finished. However, this method accesses stored data whenever the refresh operation is finished, which uses much test time and there is no way of knowing where problems, if any, occur during the refresh operation.
FIG. 1 is a waveform view describing a self refresh operation of a semiconductor memory device.
First, with a test mode signal TM1 being enabled, when the memory device enters a self refresh mode by a command EXTERNAL COMMAND inputted from outside of the semiconductor memory device, a refresh timer provided therein generates a refresh enable signal OSC every preset period. The refresh operation is carried out whenever the refresh enable signal OSC gets activated. At this time, a clock enable signal CKE is at a logic low level, which is in a deactivation state. An internal clock is internally generated by buffering a system clock CLK provided from the outside. The internal clock is inputted to a counter provided in the semiconductor memory device, wherein the counter counts the internal clock. Meanwhile, when the refresh enable signal OSC gets in an activation state, control signals 01 and 02 of pulse shape are produced at a rising edge of the refresh enable signal OSC. The control signal 01 is used to latch a value counted in the counter and the control signal 02 is used to initialize the counter.
The value counted in the counter is latched in a register R/G until the refresh enable signal OSC is activated again, and then outputted to the outside through an input/output line I/O and a data output buffer DQ. In this manner, it is possible to know the refresh state at the outside by providing the counted valued stored in the register to the outside whenever the refresh enable signal OSC is activated. As shown in FIG. 1, after the refresh enable signal OSC is activated, the value 2710 counted in the counter is outputted to the outside when the next refresh enable signal OSC is activated.
However, even though it is possible to know whether the refresh operation is performed by outputting the counted value when the refresh operation is made, it is difficult to know the accurate refresh period and the exact location where the refresh operation is performed. This happens because the counted value can be outputted to the outside whenever the refresh operation is performed.